As the technology of semiconductor fabrication progresses, the critical dimension (CD) has been reduced, making lithography processes more and more challenging. Of particular importance is the control of line width roughness (LWR) or line edge roughness (LER). Line edge or width roughness generally refers to the roughness of a width or edge of a line of material in a semiconductor device (e.g., during fabrication). Uncontrolled LWR and LER can have significant impacts on the resulting semiconductor device (e.g., transistor). These impacts include poor parametric device performance and yield, for example, and variations in critical dimension (CD), which can cause variations in current (Ioff, Idsat).
The conventional photolithography process of forming fine patterns is typically insufficient to address these concerns. There maybe limits in improving resolution, e.g., due to limits in the chemical properties of the photoresists, the wavelength or light sources, and/or resolution limits in optical systems. Therefore, a photolithography process addressing the above issues is needed.